By Charles Chiang, Jamil Kawa
This publication walks the reader via all of the facets of manufacturability and yield in a nano-CMOS procedure. It covers all CAD/CAE points of a SOC layout stream and addresses a brand new subject (DFM/DFY) severe at ninety nm and past. This e-book is a needs to learn publication the intense training IC dressmaker and a very good primer for any graduate scholar reason on having a profession in IC layout or in EDA software improvement.
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Extra resources for Design for Manufacturability and Yield for Nano-Scale CMOS (Integrated Circuits and Systems)
5 DFM and DFY: Fully Intertwined In summing up this chapter it is not hard for the reader to see the complexities associated with all aspects of the nano era IC manufacturing. Two major conclusions are self-evident. First, no single group owns the DFM and DFY responsibility, yet an oversight or the slightest error by one group or individual in the whole product flow is sufficient to either kill the product or to impact the product yield adversely and in a significant manner. It follows that close cooperation and open communications between the electronic design automation (EDA), design (including verification), mask preparation, fabrication, assembly, and testing communities is needed.
35 Example of Improving Poly Short CA and M1 Open CA critical area for poly is improved as a result of the significant increase in (a), the distance to the next adjacent poly to the right is still much larger than the modified (a) and thus it does not take much figuring to realize that there is a net improvement in the poly CA number. Similarly by widening the metal 1 around the contact (b) and metal 1 (c) it is obvious that the open CA for metal 1 is improved at practically absolutely no cost in area and practically no cost in performance.
The final optimal spacing s∗ij is s∗ij = min[Acr (i)lef t + Acr (i)right ]. 25) The change between the optimal spacing and original spacing is the movement amount for this wire in order to minimize the critical area contributed by the wire pairs between this wire and its visible neighbors.